Automated Synthesis of Energy-Efficient Reconfigurable-Precision Circuits

Energy - Efficient Management of Reconfigurable

Caches improve performance by reducing the effective memory access latency, but consume significant static and dynamic power. Just as caches cannot be simultaneously large and fast, they also cannot be both large and low power. Smaller caches consume less static power, but can degrade performance and increase dynamic power due to more misses. There is thus a tradeoff between performance and pow...

On-chip Evolutionary Synthesis of Reconfigurable Analog Computing Circuits

The paper presents a Fielri Programmable Transistor Array (FPTA), developed as an experimental platform for implementing flexible, reconjigurable amlog computing. Parasitic effects of impedect switches interconnecting transistors deteriorate the pedormance of conventional designs when mapped to the FPTA. However, working design solutwns can be obkained through a search procedure guided by evolu...

Energy Efficient Reconfigurable SRAM Using Data-Dependency

The binary values processed and stored at the intermediary stages of an algorithm are often highly correlated. Motivated in part by this observation and the ever-increasing challenge of power density for Integrated Circuit (IC) systems, a novel reconfigurable memory framework is proposed in this thesis which builds upon traditional low power techniques such as voltage scaling in order to achiev...

Design of Energy - Efficient Approximate Arithmetic Circuits

Efficient Synthesis of Linear Reversible Circuits

gates. We present an algorithm that is optimal up to a multiplicative constant, as well as Θ(log n) times faster than previous methods. While our results are primarily asymptotic, simulation results show that even for relatively small n our algorithm is faster and yields more efficient circuits than the standard method. Generically our algorithm can be interpreted as a matrix decomposition algo...